| [1]DONG J, SMITH M. A bottom-up clustering algorithm with applications to circuit partitioning in VLSI design［A］. Proceedings of ACM/IEEE Design Automation Conference[C]. Dallas,TX,USA:ACM Press,1993.755-760.
[2]KERNIGHAN B W, LIN S. An efficient heuristic procedure for partitioning graphs［J］.Bell System Technical Journal，1970,49(2): 291-307.
[3]FIDUCCIA C M, MATTHEYSES R M. A linear-time heuristic for improving network partitions［M］. 19th ACM/IEEE Design Automation Conference[C]. San Francico,CA,USA:ACM Press,1982.175-181.
[4]SANCHIS L A. Multi-way network partitioning［J］. IEEE Trans Computers,1989,38(1):62-81.
[5]DUTTA S, DENG W. A probability-based approach to VLSI circuit partitioning［A］. Proceedings of Design Automation Conference[C]. Las Vegas,USA:ACM Press,1996.100-105.
[6]KIRKPATRICK S, GELATT C D, VECCHI M P. Optimization by simulated annealing［J］.Science，1983,220(5):671-680.
[7]CHANG J Y, LIU Y C, WANG T C. Faster and bester spectral algorithms for multi-way partitioning［A］. Proceedings of Asia and South Pacific Design Automation Conference[C]. New Orleans,USA:ACM Press,1999.81-84.
[8]MOON B R, KIM C K. Dynamic embedding for genetic VLSI circuit partitioning［J］.Engineering Applications of Artificial Intelligence，1998,3(5):67-76.
[9]MOON B R, KIM C K. Genetic VLSI circuit partitioning with dynamic embedding［A］.First International Conferences on Knowledge-Based Intelligent Electronic Systems[C].Australia:IEEE Press,1997.21-23.
[10]LI Minqiang, KOU Jisong, LIN Dan, et al. Basic theory and application of
genetic algorithms［M］. Beijing：Science Press，2002（in Chinese）.［李敏强,寇纪淞,林丹,等.遗传算法的基本理论与应用［M］
.北京：科学出版社，2002.］
[11]JOHNSON D S. Optimization by simulated annealing:part 1, graph partitioning［J］. Operations Research，1989,4(23):865-892.
|
